Data processing unit which pre-fetches instructions of different

Details Data processing unit which pre-fetches instructions of different Data processing unit which pre-fetches instructions of different

1997-08-29

1999-07-20

Eng, David Y.

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

G06F 930

Patent

active

059251220

ABSTRACT:
A data processing unit including instruction queue circuits for pre-fetching instructions from a memory and an immediate generator for receiving input of immediate data of an instruction held by the instruction queue circuits to generate data whose bit size is larger than or equal to that of the immediate data, the instruction queue circuits being provided in duplication for higher-order bits and lower-order bits of the immediate generator and storing the same instructions to apply immediate data of an instruction held in the instruction queue circuit corresponding to higher-order bits of the immediate generator to higher-order bits of the immediate generator and apply immediate data of an instruction held in the instruction queue circuit corresponding to lower-order bits of the immediate generator to lower-order bits of the immediate generator.

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NEC's User's Manual for "V810.TM. 32-BIT Microprocessor", pp. 75 and 76.
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"Computer Architecture: A Quantitative Approach", written by Hennessy and Patterson, Mikkei BP, pp. 456-457.
"Computer Organization & Design: The Hardware/Software Interface", written by Patterson and Hennessy, Nikkei BP, pp. 334-335.

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