Patent
1996-02-12
1996-12-03
Treat, William M.
395412, G06F 938, G06F 1200
Patent
active
055817211
ABSTRACT:
The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register. Also provided is an instruction controller for detecting a window start pointer set instruction for setting a value to the window start pointer register, a floating point register pre-load instruction for converting the floating point register number in the instruction to a physical floating point register number by the conversion circuit from the value obtained from the value of the window start pointer register and the value of the window stride, and storing a main memory data in the physical floating point register indicated by the physical floating point register number.
REFERENCES:
patent: 4340932 (1982-07-01), Bakula et al.
patent: 5111389 (1992-05-01), McAuliffe et al.
patent: 5179674 (1993-01-01), Williams et al.
patent: 5247645 (1993-09-01), Mirza et al.
patent: 5278963 (1994-01-01), Hattersley et al.
patent: 5388235 (1995-02-01), Ikenaga et al.
patent: 5437043 (1995-07-01), Fujii et al.
patent: 5438669 (1995-08-01), Nakazawa et al.
Hennessy et al.; "Computer Architecture: A Quantitative Approach"; pp. 450-454 (1990).
Rau et al. ; "Register Allocation for Software Pipeland Loops"; pp. 283-299 (1992).
Tirumalai et al; "Parallelization of Loops with Exits On Pipelined Architectures" (1990).
Proceedings Supercomputing '92, "Pseudo Vector Processor Based on Register-Windowed Superscaler Pipeline", N. Kisaburo, et al., Minneapolis, Minnesota, Nov. 16-20, 1992, IEEE Computer Society Press.
Fujii Hiroaki
Inagami Yasuhiro
Takeda Katsumi
Wada Hideo
Coulter Kenneth R.
Hitachi , Ltd.
Treat William M.
LandOfFree
Data processing unit which can access more registers than the re does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing unit which can access more registers than the re, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing unit which can access more registers than the re will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-794246