Data processing unit including a variable bit length bypass circ

Details Data processing unit including a variable bit length bypass circ Data processing unit including a variable bit length bypass circ

1989-03-03

1992-03-31

Lee, Thomas C.

G06F 1202, G06F 1340

Patent

active

051014890

ABSTRACT:
In a data processing unit which includes first and second buses and an arithmetic and logic unit, there is provided a register file connected between the first and second buses, for storing data on the second bus. The register file includes a plurality of a register portion having a capacity equal to or exceeding a minimum data length of data processed in the ALU, and a bypass circuit connected between the first and second buses for bypassing data on the second bus to output the data to the first bus per unit of the minimum data length, the bypass circuit including a plurality of bypass lines each having the minimum data length. A control circuit controls data read from and writing to the register file per a unit of the minimum data length and controls the bypass circuit so as to bypass the data on the second bus to the first bus per a unit of the minimum data length.

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Daghir et al.; "Bypass Circuit for Receiver and Driver Delay Measurement"; IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984; pp. 4708-4709.

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