1994-07-15
1998-03-17
Harvey, Jack B.
39542102, 39542105, 395800, G06F 300
Patent
active
057297231
ABSTRACT:
A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.
REFERENCES:
patent: 4340932 (1982-07-01), Bakula et al.
patent: 4435753 (1984-03-01), Rizzi
patent: 5111389 (1992-05-01), McAuliffe et al.
patent: 5179674 (1993-01-01), Williams et al.
patent: 5247645 (1993-09-01), Mirza et al.
patent: 5278963 (1994-01-01), Hattersley et al.
patent: 5367651 (1994-11-01), Smith et al.
patent: 5388235 (1995-02-01), Ikenaga et al.
patent: 5437043 (1995-07-01), Fujii et al.
patent: 5438669 (1995-08-01), Nakazawa et al.
Structured Computer Organization, Andrew S. Tanenbaum. 1990 pp. 11-13.
Kateuenis Thesis 1984 pp. 138-145.
Proceedings Supercomputing '92, "Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline", N. Kisaburo, et al., Minneapolis, Minnesota, Nov. 16-20, 1992, IEEE Computer Society Press.
"Computer Architecture : A Quantitative Approach", Hennesy and D. A. Patterson, Morgan Kaufmann Publishers, Inc. (1990) pp. 450-454.
"Register Allocation for Software Pipelined Loops", B. R. Rau et al. ACM Sigplan 92, pp. 238-299.
"Parallelization of Loops with Exits on Pipelined Architectures", P. Tirumalai et al., Supercomputing, 1990, pp. 200-212.
Fujii Hiroaki
Inagami Yasuhiro
Takeda Katsumi
Wada Hideo
Harvey Jack B.
Hitachi , Ltd.
Myers Paul R.
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