Data processing technique for computer color graphic system

Details Data processing technique for computer color graphic system Data processing technique for computer color graphic system

1983-06-13

1986-06-17

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340798, 364521, G09G 128

Patent

active

045959170

ABSTRACT:
A frame buffer, divided into three bit planes, is addressed by a single grahic display control chip, whose address signal is altered by an adder to address each bit plane at successive, prescribed time intervals during a single display cycle. A data word of N-bits from each of the first two bit planes is read and latched, then loaded simultaneously with a data word of N-bits from the third bit plane into corresponding shift registers. Thus, the number of memory chips in the frame buffer is minimized and three times the normal data output is achieved during each display cycle.

REFERENCES:
patent: 4016544 (1977-04-01), Morita et al.
patent: 4150364 (1979-04-01), Boltzer
patent: 4183046 (1980-01-01), Dalke et al.
patent: 4217577 (1980-08-01), Roe et al.
patent: 4408223 (1983-10-01), Midland

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