Data processing system with shared control signals and a state m

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395200, 395575, 364221, 3642216, 3642217, G06F 100

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active

052768570

ABSTRACT:
Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

REFERENCES:
patent: 4622669 (1986-11-01), Pri-Tal
patent: 5126950 (1992-06-01), Rees et al.
patent: 5157781 (1992-10-01), Harwood et al.

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