Data processing system with multiple execution units capable of

Details Data processing system with multiple execution units capable of Data processing system with multiple execution units capable of

1991-08-26

1994-11-08

Lall, Parshotam S.

395800, G06F 938

Patent

active

053634950

ABSTRACT:
A data processing system is provided that includes a plurality of execution units each including independent circuits for storing and executing instructions. A circuit is also included for providing instructions from a sequence of instructions to the execution units where each instruction is provided to only one of the execution units. The system includes a circuit for detecting when an instruction in a first execution unit must complete execution prior to execution of an instruction in a second execution unit to produce correct results. A circuit is further included, responsive to the circuit for detecting, for delaying executing the instruction in the second execution unit until the instruction in the first execution unit has completed execution.

REFERENCES:
patent: 3447135 (1969-05-01), Calta et al.
patent: 3588829 (1971-06-01), Boland et al.
patent: 3949379 (1976-04-01), Ball
patent: 3962706 (1976-06-01), Dennis et al.
patent: 3997896 (1976-12-01), Cassarino, Jr. et al.
patent: 4128882 (1978-12-01), Dennis
patent: 4130885 (1978-12-01), Dennis
patent: 4153932 (1979-05-01), Dennis et al.
patent: 4181934 (1980-01-01), Marenin
patent: 4232366 (1989-11-01), Levy et al.
patent: 4370710 (1983-01-01), Kroft
patent: 4376976 (1983-03-01), Lahti et al.
patent: 4507728 (1985-03-01), Sakamoto et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4626989 (1986-12-01), Torii
patent: 4630195 (1986-12-01), Hester et al.
patent: 4675806 (1987-06-01), Uchida
patent: 4734852 (1988-03-01), Johnson et al.
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4763294 (1988-08-01), Fong
patent: 4773041 (1988-09-01), Hassler et al.
patent: 4855947 (1989-08-01), Zmyslowski et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4916606 (1990-04-01), Yamaoka et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 4942525 (1990-06-01), Shintani et al.
patent: 4956800 (1990-12-01), Kametani
patent: 5075840 (1991-12-01), Grohoski
patent: 5093908 (1992-03-01), Beacom et al.
patent: 5133077 (1992-06-01), Karne et al.
patent: 5150469 (1992-09-01), Jouppi
patent: 5150470 (1992-09-01), Hicks et al.
patent: 5197137 (1993-03-01), Kumar et al.
patent: 5214763 (1993-05-01), Blaner et al.
Proceedings, Twentieth Annual Allerton Conference on Communication, Control, and Computing, H. V. Poor et al, Conference held Oct. 6-8, 1982, Allerton House, Monticello, Ill., pp. 577-586.
IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, pp. 136-137, "New Condition Code and Branch Architecture for High Performance Processors".
IBM Technical Disclosure Bulletin, vol. 29, No. 7, Dec. 1986, pp. 3176-3177, "Condition Code Facility".
IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988, pp. 294-296, "Multiple Queued Condition Codes".
IBM Technical Disclosure Bulletin, vol. 32, No. 7, Dec. 1989, pp. 109-113, "Device for Synchronizing Multiple Processors".
"The 801 Minicomputer" by George Radin, first published in ACM Sigarch Computer Architecture News, vol. 10, No. 2; also published in IBM Journal of Research and Development, vol. 27, No. 3, pp. 237-246, May 1983.
"Data-Flow IC Makes Short Work of Tough Processing Chores", Electronic Design, May, 17, 1984, pp. 191-206.
"A Preliminary Architecture for a Basic Data-Flow Processor" by Jack Dennis and David Misunas, published by IEEE in the Proceedings of the 2nd Annual Symposium on Computer Architecture, 1975, pp. 126-132.
"A Data Flow Multiprocessor", IEEE Transactions on Computers by James Rumbaugh, vol. C-26, No. 2, Feb. 1977, pp. 138-146.
"The Piecewise Data Flow Architecture: Architectural Concepts", IEEE Transactions on Computers, vol. C-32, No. 5, May 1983, pp. 425-438.
The Data Control 6600 by Thornton, pp. 6-7 and 124-141.
"The Metaflow Architecture", Popescu et al, IEEE pp. 10-13, 63-73, Jun. 1991.

Affiliated with

Also associated with

Rating

Data processing system with multiple execution units capable of does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing system with multiple execution units capable of , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system with multiple execution units capable of will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1789596