Boots – shoes – and leggings
Patent
1991-11-21
1993-06-08
Kulik, Paul V.
Boots, shoes, and leggings
395725, 395800, 364DIG1, 364243, 3642431, 3642426, 3642427, 36424291, 3642281, 364229, 364238, 3642384, G06F 1318, G06F 1516
Patent
active
052186881
ABSTRACT:
In a data processing system including a plurality of multi-processor systems, each multi-processor system having at least one central processing unit and at least one main memory both connected to a memory control unit, each memory control unit is connected to each other memory control unit, the memory control unit comprises plural ports, plural registers, access selection circuits for innner and outer access, a priority control circuit, a first and a second control circuit, and wait signal reset circuit, a priority of accesses from the same central processing unit to the other multi-processor system is detected, and the registers to store the access request signals in the other multi-processor system are efficiently used by adding a priority control signal to the access request signal. Thus, the data throughput of the system and the speed of the access are improved.
REFERENCES:
patent: 4718006 (1988-01-01), Nishida
S. Horiguchi et al.: "Throughput of multiprocessor systems with common memories", Transactions of the I.E.C.E. of Japan, vol. E69, No. 6, Jun. 1986, pp. 726-729, Tokyo, Japan.
Fujitsu Limited
Kulik Paul V.
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