Data processing system with master and slave processors

Electrical computers and digital processing systems: multicomput – Master/slave computer controlling

Reexamination Certificate

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C709S213000, C712S031000

Reexamination Certificate

active

06907454

ABSTRACT:
A data processing system comprises a master processor (10), a slave processor (30), a memory (50), and a bus subsystem (20) interconnecting the master processor (10), the slave processor (30), and the memory (50). The master processor (10) is configured to generate, in response to a memory access instruction, a read request comprising a read command for execution by the slave processor (30) to read data stored in a location in the memory (50) specified by the memory access instruction, and to write the read request to the slave processor (30) via the bus subsystem (20). The slave processor (30) is configured to execute the read command received in the read request from the master processor (10) to obtain the data stored at the specified location in the memory (50) and to write the data thus obtained to the master processor (10) via the bus subsystem (20).

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