Data processing system with instruction queue having tags indica

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Details

364DIG1, 3642394, 3642584, 3642628, G06F 930

Patent

active

051504707

ABSTRACT:
A data processing system having an instruction execution circuit that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

REFERENCES:
patent: 4179736 (1979-12-01), Wilhite
patent: 4675806 (1987-01-01), Uchida et al.
patent: 4953082 (1990-08-01), Nomura et al.
patent: 4972317 (1990-11-01), Buonomo et al.
patent: 4999802 (1991-03-01), Cocanougher et al.
patent: 5001624 (1991-03-01), Hoffman et al.
patent: 5045992 (1991-03-01), Yates et al.

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