Data processing system with coprocessor

Details Data processing system with coprocessor Data processing system with coprocessor

1987-03-02

1990-01-16

Shaw, Gareth D.

Boots, shoes, and leggings

3642286, 3642615, G06F 1300, G06F 1516

Patent

active

048947687

ABSTRACT:
When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.

REFERENCES:
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4547849 (1985-10-01), Louie et al.
patent: 4598356 (1986-07-01), Dean et al.
patent: 4648034 (1987-03-01), Heninger
patent: 4731736 (1988-03-01), Mothersole et al.
patent: 4777613 (1988-10-01), Shahan et al.
MC68020 32-Bit Microprocessor User's Manual, second edition, 1985, pp. 8-1 to 8-57 and pp. 9-26.

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