Data processing system with condition code architecture for exec

Details Data processing system with condition code architecture for exec Data processing system with condition code architecture for exec

1992-10-16

1995-08-08

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364258, 3642581, 3642582, 364259, 3642592, 3649371, G06F 748

Patent

active

054407028

ABSTRACT:
A data processing system having a mathematically consistent condition code architecture is disclosed for implementing single instruction range checking and limiting operations. The data processing system includes condition code flags that are set to provide indications of the occurrence of arithmetic overflow and the direction of the arithmetic overflow for all of the possible arithmetic operations that can be performed by an arithmetic logic unit within the digital processing system. Based upon the indicated occurrence of arithmetic overflow and the direction of the overflow, the numeric value of a software variable generated by one of the arithmetic operations is limited to an appropriate upper or lower bound of a predetermined range of acceptable values, if the numeric value was generated with the occurrence of arithmetic overflow, or the numeric value was generated without the occurrence of overflow, but was outside of the acceptable range of values.

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