Data processing system which selectively bypasses a cache memory

Details Data processing system which selectively bypasses a cache memory Data processing system which selectively bypasses a cache memory

1985-08-23

1990-06-26

Lee, Thomas C.

Boots, shoes, and leggings

36424341, 36424343, 3642548, 3642611, G06I 1202

Patent

active

049377388

ABSTRACT:
A cache memory contained in a processor features a high efficiency in spite of its small capacity.
In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.
By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

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