Data processing system simultaneously performing plural translat

Details Data processing system simultaneously performing plural translat Data processing system simultaneously performing plural translat

1992-12-14

1995-07-04

Harvey, Jack B.

Boots, shoes, and leggings

3642321, 3642434, 3642551, 3642557, 3642563, 3642564, 364DIG1, G06F 1206, G06F 1208, G06F 1210

Patent

active

054308569

ABSTRACT:
A data processing system which is capable of performing simultaneously multiple address translation of logical addresses of different page sizes into corresponding physical addresses. The system includes a processor, a main storage area, which is logically partitioned into a number of partial spaces, and an address translation controller for translating logical addresses output by the processor to physical addresses which correspond to partial spaces of the main storage area.

REFERENCES:
patent: 4376297 (1983-03-01), Anderson et al.
patent: 4691281 (1987-09-01), Furui
patent: 4835734 (1989-05-01), Kodaira et al.
patent: 5058003 (1991-10-01), White
patent: 5278963 (1994-01-01), Hattersly et al.
Plant et al IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1976, pp. 57-60, "Page Boundary Crossing Detection Hardware".

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