Data processing system providing split bus cycle operation

Communications: electrical – Digital comparator systems

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G06F 1300

Patent

active

039978966

ABSTRACT:
In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively in an interleaved manner.

REFERENCES:
patent: 3478321 (1969-11-01), Cooper et al.
patent: 3710324 (1973-01-01), Cohen et al.
patent: 3866181 (1975-02-01), Gayman et al.
patent: 3886524 (1975-05-01), Appelt

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