Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-11-29
2003-11-18
Le, Thong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S203000
Reexamination Certificate
active
06650592
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of timing tools executing by data processing systems, and more specifically to a system, method, and product for automatically performing timing checks on a memory cell using a static timing tool.
2. Description of Related Art
FIG. 1
is a schematic diagram of a two-bit static RAM circuit in accordance with the prior art. The two input pins at the top of the diagram are labeled din (for data in) and din_b (for data in bar) and represent the true and complement data respectively to be written into the selected memory cell. Signals din and din_b are connected to tri-state buffer/driver TR
0
and TR
1
respectively. The other input connected to TR
0
and TR
0
is write enable (wen). Bit line (bl) and its complement bit line bar (bl_b) are the outputs of TR
0
and TR
1
respectively and present true and complement write data during the write operation. CELL
0
and CELL
1
are a one bit memory cell each, where block CELL
0
contains the same circuitry as the detailed view in CELL
1
.
CELL
1
consists of p-channel devices Q
21
and Q
23
and n-channel devices Q
20
, Q
22
, Q
24
and Q
25
. Where Q
21
and Q
22
form one inverter and Q
23
and Q
24
form another inverter. Both inverters are configured in such a way that their outputs are connected to the input of the other inverter, thus forming a latching circuit. Q
20
and Q
25
are configured as pass transistors and are responsible for passing the data in and out of the memory cell. Word lines wl_
0
and wl_
1
respectively are outputs of DEC
0
and DEC
1
(2×2 AND OR circuits) respectively. In the following example the operation of DEC
1
is described.
If input wrsel<
1
> and input wen go high, the SRAM enters the write operation for CELL
1
. It should be noted that the addressing scheme described here is only used for illustration purposes and implies that a decoder (not shown) guarantees the orthorgonality of wrsel<
0
> and wrsel <
1
>. Hence only one “row” of cells may be written to with each write access. The “row” of cells is represented here by CELL
1
. An SRAM, however, may be configured such that a row consists of a byte, a word, or any other practical number of bits. It is further implied that the input signals ren (read enable) and pc (pre-charge) are low and high respectively during the write operation.
Inverter INV then drives ren_b high turning off p-channel transistors Q
11
and Q
10
disconnection the bit lines bl and bl_b from the sense amplifier S_AMP. As wen goes high the tri-state buffer/drivers turn on and valid true and complement write data is driven onto the bl and bl_b regardless of their previous state. Depending upon the arrival time of wrsel<
1
>, wl_
1
goes active (high) at least one delay time through DEC
1
after wen has gone high (active). This turns on n-channel pass transistors Q
20
and Q
25
and data from bl and bl_b is overwriting the cell data (bl_c and bl_c_b). When wl_
1
goes low, the write operation is completed and Q
20
and Q
25
turn off again.
Prior to reading from the cell a pre-charge operation must be performed. For this function ren and wen must be low such that wl_
0
and wl_
1
are both low and the memory cells are isolated from the bit lines. Hence tri-state drivers/buffers TR
0
and TR
1
are in their high impedance state. Pre-charge begins when pc goes low turning on p-channel devices Q
12
, Q
13
, Q
18
, Q
9
, Q
8
, Q
7
and Q
10
and bit lines bl and bl_b and sense amp bit lines bl_s and bl_s_b are pre-charged to Vdd. The purpose of Q
13
and Q
8
is to ensure that the true and complement bit lines receive equal amount of charges. Inactivating pc (pulling high) terminates the pre-charge operation and the SRAM is in standby mode and ready to be read.
Similar to the write operation reading is performed by making the word line wl_o or wl_
1
valid. Again only one “row” may be selected and wen must be low keeping TR
0
and TR
1
in their high impedance state. Reading CELL
1
is accomplished by driving both rdsel<
1
> and ren high. This activates word line wl_
1
and pass devices Q
20
and Q
25
are turned on. Furthermore ren is connected to inverter INV. The inverted output of INV (ren_b) goes low and turns on Q
11
and Q
10
switching together bl and bl_s and bl_b and bl_s_b respectively. True and complement data that is stored as bl_c and bl_c_b in CELL
1
during writing is now passed through respective pass transistors Q
20
and Q
25
onto bl and bl_b respectively.
If a logic zero was stored in the cell true stored data bl is low and complement stored data bl_c_b is high and since bl_b has been pre-charged to Vdd it remains at a high level. Since true stored data is low (bl_c), bl starts to be discharged from its pre-charge Vdd level towards ground through Q
20
and Q
22
. Sense amplifier enable signal se is timed such that it goes high when during a read operation bl (bl_s) or bl_b (bl
—s
_b) has been discharged to a predetermined level (e.g. 20%) below Vdd. Sense amplifier S_AMP consists of p-device Q
4
and Q
5
and n-devices Q
1
through
3
, where Q
2
through Q
5
are configured similar to CELL
1
as a cross coupled inverter latch. Q
1
is the control transistor for se. Once se is high and Q
1
is on, the sense amplifier will switch at its threshold which is typically when bl has fallen to 80% of its pre-charge value and helps to discharge bl_s through Q
2
and Q
1
and therefore bl through Q
11
. True and complement bit lines (bl and bl_b) are connected to the system through buffer/drivers BUFF_T and BUFF_C respectively (data and data_b). While it is only discharged through the memory cell the slope is small. As soon as se turns on Q
1
, the discharge slope becomes significantly faster.
Static timing tools have been developed to verify the timing in large logic circuits efficiently. They enable timing analysis without extensive functional pattern generation. But the tools are not always able to “understand” how certain circuits are supposed to function.
Static timing tools include standard timing elements. Each standard timing element has associated with it one or more standard timing checks. When one of these timing elements is encountered, the associated timing check(s) are performed by the static timing tool. As an example, static timing tools include a pre-charge timing element, a latch timing element, and a gated clock timing element.
Static timing tools have not been used to verify timing in memory cells included in particular static random access memory (SRAM) devices. The standard timing elements have not been used before to verify timing in SRAMs because the standard timing elements are engaged when certain circuit structures are present. The RAM circuit structures do not match those that are standard in the static timing tools. The RAM defies the timing tool's ability to find the RAM structures because in the RAM the pre-charge and latching mechanisms are too complicated for the timing tool to parse. For example, in the RAM (1) the latch is dual rail, and (2) the node bl is bi-directional. For instance, bl_c and bl_c_b are complementary storage nodes for the same cells. The static timing tools assume latches do not have complementary storage cells.
Therefore, a need exists for a system, method, and product for automatically performing timing checks on a memory cell using a static timing tool.
SUMMARY OF THE INVENTION
A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.
The above as well as additional objectives, features, and advantages of the present invention
Amatangelo Matthew J.
Durham Christopher M.
Klim Peter Juergen
International Business Machines - Corporation
Le Thong
McBurney Mark E.
Yee Duke W.
Yociss Lisa L. B.
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