Data processing system including cache memory for rapidly conver

Details Data processing system including cache memory for rapidly conver Data processing system including cache memory for rapidly conver

1989-05-31

1994-01-04

Harrell, Robert B.

Boots, shoes, and leggings

3642433, 3642543, 3642555, 3642551, 364DIG1, G06F 1206

Patent

active

052768295

ABSTRACT:
In a data processing system including a logical address cache memory device, a plurality of logical address areas are assigned to a shared physical address area. A shared memory flag representing whether the physical address area represented by each address conversion information is part of the shared memory area is added to the address conversion information used in address conversion by the physical address coincidence detection mechanism. When a cache miss is detected in the logical address cache memory device, the physical address coincidence detection mechanism performs first address conversion for converting a predetermined field of the logical address required upon a main memory access request into an upper physical address. When the shared memory flag of the address conversion information used in the first address conversion is true, the physical address coincidence detection mechanism performs second address conversion for converting an address tag of tag information read out from the main memory into an upper physical address during cache memory access upon a main memory access request, and detection of a coincidence between the first and second address conversion results.

REFERENCES:
patent: 4622631 (1986-11-01), Frank
patent: 4742450 (1988-05-01), Duvall
patent: 4843542 (1989-06-01), Dashiell
patent: 4939641 (1990-07-01), Schwartz

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