Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1999-12-13
2001-07-03
Hjerpe, Richard (Department: 2674)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S023000, C712S011000, C709S213000, C709S214000, C709S215000
Reexamination Certificate
active
06256722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a novel multiprocessor distributed memory system providing high-speed deterministic system connectivity, a novel PCI-based printed circuit board and methods therefor.
2. State of The Prior Art
Multiprocessor distributed memory systems are known and currently in wide use in the art. Such systems are characterized by certain deficiencies and can be substantially improved. For example, present systems essentially arbitrate resources in software and are slow in this respect. Since such systems are configured as loops or rings, if it is necessary to remove one of the processors, or as it is commonly referred to a node, from the loop or ring, this can only be effected by powering down the entire ring. In current systems, DMA transfers need to be sent around the entire ring thereby wasting bandwidth by transmitting past the targeted receiving node. Further, with the adoption of the PCI bus standards in PC technology, there exists a need in the art to support an effective distributed memory system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a distributed memory system that will overcome the deficiencies and disadvantages of present known systems, and that will function more efficaciously and efficiently. Also, the present invention provides a novel printed circuit board that can be used in a system that includes PCI buses. The novel system of the present invention can be implemented in an electrical loop or ring or in an optical fiber loop or ring to achieve high performance and low latency by using master/master ring topology, up to 256 point-to-point flow controlled segments which can be configured to form an electrical ring up to 7.5 km in circumference or perimeter (100 feet between nodes, up to 256 nodes) or an optical ring about 750 km in circumference or perimeter. One of the principal advantages of the present invention is the ability to transfer simultaneously data from every node to traverse the entire ring (multipoint-to-multipoint). The 256 nodes are able to broadcast and receive at a given instance in time without tokens or data collisions in less than 300 microseconds. By the system of the present invention data transfers are obtainable of up to 1 Gigabaud per second with the lowest cost per connection thereby providing the capability of moving data at 100 MB per second using the fiber channel level
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coding scheme as known in the art.
The foregoing is accomplished by the present invention, in the development of a specific application of the invention by providing a unique PCI-Fiber Channel Memory Channel (PCI-FCMC) system for interconnecting standard 33 MHz PCI processor system buses to a serial Memory Channel. A novel PCI-FCMC board is provided as an element of the present invention which is a standard Type-5 form factor PCI card that occupies a single PCI slot in a standard type PC-style motherboard. The novel PCI-FCMC board provides the ability to share memory areas from within the on board memory area, from external to the board's memory area, along with the ability to provide a unique arbitration methodology. Some unique features of this novel and inventive board are a loop polling command, a DMA command queue, the ability to provide a dynamic insertion and removal of boards within an operating loop in the copper or fiber based buses without restarting the entire system, the ability to use DMA for memory areas reflected between two or more nodes, and the ability to stimulate ‘Mailbox style’ interrupts through the Memory Channel bus. The inventive PCI-FCMC board acts in the system like a standard memory card. Different areas of the Memory array provide different functions which provide the unique variety of features provided by this invention as will become more evident from the following description of the preferred embodiment. The 64 or 128 MByte memory array within the board provides internal shared memory between systems. 4 KB areas, while they are mapped physically within the 64 or 128 MByte memory array, can provide a function of arbitration if a configuration bit is set. Additionally the board has the ability to provide DMA driven reflected memory from any portion of the remaining addressable area of memory within the system.
A data processing system has been created comprising, a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node including; a processor, a printed circuit board, a memory partitioned into a plurality of sections, a first section for directly sharable memory located on the printed circuit card, and a second section for block sharable memory, a local bus connecting the processor, the block sharable memory, and the printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board, and the printed circuit board having; a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial bus to next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.
A data processing system has been created comprising; a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node including; a processor, a printed circuit board, a memory for block sharable memory, a local bus connecting the block sharable memory and the printed circuit board, for transferring data from the block sharable memory to the printed circuit board; and the printed circuit board having; a memory moving device for reading data from the block sharable memory, a queuing device for queuing the read data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial bus to next successive processing node, a receiver for receiving serialized data from next preceding processing node, a deserializer for deserializing the received serialized data into parallel data.
A data processing system has been created comprising; a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node including; a processor, a printed circuit board, a memory for block sharable memory, a local bus connecting the block sharable memory and the printed circuit board, for transferring data from the block sharable memory to the printed circuit board, and the printed circuit board having; a node ID, a memory moving device for reading data from the block sharable memory, a tagging device for tagging the block transfer with a transfer tag and destination node ID tag, a queuing device for queuing the tagged data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial bus to next successive processing node, a receiver for receiving serialized data from next preceding processing node, a deserializer for deserializing the received serialized data into parallel data, a first sensor for detecting the transfer tag, a second sensor for sensing the destination tag within the parallel data, a comparator for comparing second sensed destination tag with the node destination ID, a routing device for steering the parallel data to the transmitter if the first sensor indicates the presence of the sensed tag and comparator is not true, and a second routing device for steering parallel data to the memory if the first sensor indicates the presence of the sensed tag and comparator is true.
A data processing system ha
Acton John D.
Derbish Michael D.
DeRolf William B.
Gibson Gavin G.
Hardy, Jr. Jack M.
Conleey, Rose & Tayon, PC
Hjerpe Richard
Kivlin B. Noäl
Monestime Mackly
Sun Microsystems Inc.
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