Data processing system including a cache memory

Details Data processing system including a cache memory Data processing system including a cache memory

1978-06-08

1980-04-08

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1306

Patent

active

041975804

ABSTRACT:
A data processing system includes a memory arrangement comprising a main memory, and a cache memory including a validity bit per storage location to indicate the validity of data stored therein. Cache performance is improved by a special read operation to eliminate storage of data otherwise purged by a replacement scheme. A special read removes cache data after it is read and does not write data read from the main memory into the cache. Additional operations include: normal read, where data is read from the cache memory if available, or, from main memory and written into cache; normal write, where data is written into main memory and the cache is interrogated, in the event of a hit, the data is either updated or effectively removed from the cache by invalidating its associated validity bit; and special write, where data is written both into main memory and the cache.

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patent: 3611315 (1971-10-01), Murano et al.
patent: 3735360 (1973-05-01), Anderson et al.
patent: 3840862 (1974-10-01), Ready
patent: 3949368 (1976-04-01), West
patent: 3979726 (1976-09-01), Lange et al.
patent: 3984818 (1976-10-01), Gnadeberg et al.
patent: 4075686 (1978-02-01), Calle et al.

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