Boots – shoes – and leggings
Patent
1983-10-28
1990-02-13
Harkcom, Gary V.
Boots, shoes, and leggings
364748, G06F 748, G06F 922, G06F 1204
Patent
active
049012355
ABSTRACT:
A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.
REFERENCES:
patent: 4371925 (1983-02-01), Carberry et al.
patent: 4476523 (1984-10-01), Beanchamp
patent: 4476537 (1984-10-01), Blau et al.
Computer Design, Mar. 1981, pp. 178-182, "Floating Point Microprocessor Implemented as Optical Co-Processor".
Computer Design, Oct. 1979, pp. 182-186, "Floating Point Chip Performs 32- and 64-Bit Operations".
Hecker Mark B.
Murdoch Robert N.
Vora Chandra R.
Wiser Donald C.
Data General Corporation
Harkcom Gary V.
Lynt Christopher H.
O'Connell Robert F.
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