Boots – shoes – and leggings
Patent
1983-10-28
1986-11-11
Shaw, Gareth D.
Boots, shoes, and leggings
364900, G06F 900
Patent
active
046226303
ABSTRACT:
In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.
REFERENCES:
patent: 4292668 (1981-09-01), Miller et al.
patent: 4300194 (1981-11-01), Bradley et al.
patent: 4316244 (1982-02-01), Grondalski
patent: 4371925 (1983-02-01), Carberry et al.
Bagula Mark
Hamilton Steve
Vora Chandra R.
Ziegler Michael L.
Data General Corporation
Mills John G.
O'Connell Robert F.
Shaw Gareth D.
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