Data processing system having synchronous bus wait/retry cycle

Details Data processing system having synchronous bus wait/retry cycle Data processing system having synchronous bus wait/retry cycle

1982-01-15

1985-01-22

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 304, G06F 1300

Patent

active

044955715

ABSTRACT:
A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

REFERENCES:
patent: 3993981 (1976-11-01), Cassarino
patent: 4038642 (1977-07-01), Bouknecht
patent: 4067059 (1978-01-01), Derchak

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