Data processing system having serial self address decoding and m

Details Data processing system having serial self address decoding and m Data processing system having serial self address decoding and m

1993-12-27

1994-09-13

Beausoliel, Jr., Robert W.

Excavating

371 151, 371 221, H04B 1700

Patent

active

053475232

ABSTRACT:
A data processing system (90) having a serial scan circuit (10). The serial scan circuit (10) has an address detector (12) for detecting and decoding M serially-provided address bits. Coupled to the address detector (12) is a clock generator (14) which is used for providing at least one derived clock signal. Coupled to the address detector (12) and the clock generator (14) is a serial scan chain (16) which is used to store N serially-provided data bits. A plurality of serial scan chains (10) is connected in a parallel configuration and used to form the data processing system (90). The M address bits and the N data bits are serially provided via a single conductor (24) in a time division multiplexed operation. Integrated circuit surface area is reduced by avoiding large address and data buses, and bus routing.

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