Excavating
Patent
1990-11-19
1993-05-11
Beausoliel, Jr., Robert W.
Excavating
371 221, 371 225, G06F 1122, G01R 3128
Patent
active
052107590
ABSTRACT:
A data processing system uses a scannable test circuit to provide transistor fault testing of a large amount of random transistor logic. In a test mode of operation, a plurality of Master-Slave latches are used to observe the output of a plurality of data path drivers activated during a scan test operation. The data path drivers are included as part of the random transistor logic, and the outputs of the data path drivers are connected to a set input of the Master portion of one of a plurality of Master-Slave latches. The Master-Slave latches can be scanned to provide a test signal providing transistor fault information in the data processing system.
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Generalized Scan Test Technique For VLSI Circuits (IBM Technical Disclosure Bulletin vol. 28 No. 4), Sep. 1985, 1600-1604.
DeWitt Bernard C.
Gallup Michael G.
Beausoliel, Jr. Robert W.
King Robert L.
Motorola Inc.
Snyder Glenn
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