Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-11-23
2003-03-18
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S245000, C712S228000, C712S035000, C709S241000, C709S241000, C709S241000, C709S241000
Reexamination Certificate
active
06535971
ABSTRACT:
The present application is based on application Nos. 10-333039 and 10-357732 filed in Japan, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a data processing system, and more particularly, to a data processing system in which a plurality of serially connected processing portions execute respective parts of a series of processings asynchronously to input data.
2. Description of the Related Art
FIG. 44
is a block diagram showing the general configuration of a synchronous pipeline type data processing apparatus as a first conventional technique. The conventional data processing apparatus includes an MPU
70
, an image input device
71
, processing portions
72
to
76
to execute five processings, SH correction, Log conversion, MTF correction, gamma correction and binarization, respectively and an image output device
77
. Image input device
71
includes a photoelectric conversion element such as CCD, a driving system operating the same, and an A/D converter, scans a document for example including both a continuous tone image and line drawing to generate a sampled analog signal, and quantizes the sampled analog signal using the A/D converter into continuous tone reflectivity data in which each pixel has 8 bits (256 tones), for output as a digital signal.
Processing portion
72
performs SH correction processing. The SH correction is also called “shading correction”, and is a correction processing to remove reading variations (shading variations) caused by variations in the performance in the photoelectric conversion element such as CCD in image input device
71
.
Processing portion
73
performs Log conversion processing. The Log conversion is a processing to calculate and output 8-bit continuous tone density data in the Log relation with the continuous tone reflectivity data after the SH correction.
Processing portion
74
performs MTF correction processing. The MTF correction is performed to correct sharpness, and the sharpness of the 8-bit continuous tone density data obtained by executing the Log conversion to image data at processing portion
73
is corrected using a digital filter such as a Laplacian filter.
Processing portion
75
performs gamma correction processing. The gamma correction is performed to correct the difference in the tone curve between image input device
71
and image output device
77
so as to realize a desired gamma characteristic for the entire data processing apparatus. For example, using an LUT (Look Up Table) of 256 words, 8 bits, non-linear gamma correction data is output. The gamma correction may be also performed to set a desired gamma characteristic for the operator.
Processing portion
76
performs binarizing processing. The binarizing is performed to convert 8-bit continuous tone density data subjected to the gamma correction into 1-bit binary data corresponding to the brightness. The binarizing processing employs area-type tone binarizing such as error diffusion binarizing.
Image output device
77
is a printer such as an electrophotographic printer or ink jet printer, and prints the 1-bit binary data formed by binarization at processing portion
76
onto an output medium such as paper.
Image input device
71
, processing portions
72
to
76
and image output device
77
are connected through an image data bus, and process data input in synchronization with a pixel clock common to them.
Thus, in the synchronous pipeline type data processing apparatus described in conjunction with the first conventional technique, image data input from image input device
71
is sequentially processed by processing portions
72
to
76
on a pixel data piece basis. In order to achieve synchronism in exchange of the pixel data among image input device
71
, processing portions
72
to
76
, and image output device
77
, a pixel clock corresponding to each piece of pixel data is generated by a clock generator (not shown), and image input device
71
, processing portions
72
to
76
, and image output device
77
operate in synchronization with the pixel clock.
As a second conventional technique, the five processings described in conjunction with the first conventional technique are executed asynchronously.
FIG. 45
is a block diagram showing the asynchronous processing method. Referring to
FIG. 45
, processing blocks
80
,
81
and
82
can perform processings in response to clocks
85
,
86
and
87
specific to them. However, since the processing blocks operate without synchronization, data cannot be exchanged directly among the processing blocks. Thus, buffer memories
83
and
84
having a prescribed capacity are necessary among the blocks. This is because buffer memories
83
and
84
can absorb the difference in the processing speeds of processing blocks
80
,
81
and
82
.
Furthermore, as a third conventional technique, there is a parallel processing method in which the same processings are performed in parallel. For example, according to a technique disclosed by Japanese Patent Laying-Open No. 61-28164, provided is a pipeline processor having a plurality of image pipeline processors which are connected in a ring for parallel processing and task (image data), an object program for each task, and a table for each task are loaded from the memory to the pipeline processor. The pipeline processor processes prescribed tasks in parallel.
In the synchronous pipeline type data processing apparatus described in conjunction with the first conventional technique, image input device
71
, processing blocks
72
to
76
and image output device
77
operate in synchronization with a pixel clock, and the pixel clock must be generated based on any element having the lowest operating speed among image input device
71
, processing portions
72
to
76
, and image output device
77
. As a result, the circuit must be constructed according to a processing portion forming a bottleneck (having the lowest operating speed), which makes difficult the circuit design.
Furthermore, in the asynchronous processing type data processing apparatus described in conjunction with the second conventional technique, a processing block forming a bottleneck would not determine the processing speed of the data processing apparatus unlike the case of the synchronous pipeline method described in conjunction with the first conventional technique, but buffer memories are necessary, which pushes up the cost. In addition, since data is written/read to/from the buffer memory by two processing blocks, each block must accommodate such that one of the blocks can access a buffer memory, or such an arbitration processing must be performed by a controller provided for each of the buffer memories.
Furthermore, in the parallel processing method described in conjunction with the third conventional technique, a processing with a large processing load is processed by a plurality of processing blocks connected in parallel, and therefore high speed processing can be performed, but excess processing blocks to execute a processing with a large load are previously added. As a result, if the load of a processing block changes based on input data, one of processing blocks connected in parallel is not used when the load is small, which lowers the performance of the apparatus.
Also as a fourth conventional technique, an asynchronous type data processing apparatus to sequentially execute a plurality of processings to input data using a plurality of MPUs (micro processing units) is known. In the conventional data processing apparatus, the plurality of MPUs execute respective parts of the plurality of processings for asynchronous data processing, and data is exchanged among the MPUs to execute the series of processings to the input data.
FIG. 46
is a block diagram for use in illustration of data input/output between MPUs in the conventional data processing apparatus. The figure shows data input/output in executing 10 processings, processings
1
to
10
by two MPUs, MPUs
121
and
122
. MPU
121
executes 5
Ishikawa Atsushi
Sawada Kenichi
Shirasawa Toshiya
Burns Doane , Swecker, Mathis LLP
Minolta Co. , Ltd.
Pan Daniel H.
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