Data processing system having no bus utilization priority contro

Details Data processing system having no bus utilization priority contro Data processing system having no bus utilization priority contro

1984-04-09

1986-12-23

Eng, David Y.

Boots, shoes, and leggings

G06F 1336

Patent

active

046316698

ABSTRACT:
In order to ensure that separately arranged instruction processing and execution units do not use the same bus and the same time, and to eliminate the need for a multiplexer, when the execution unit requires the use of the bus, a pause signal is fed to the instruction processing unit to temporarily disable a processing portion involved therein in case the both units use the same bus concurrently.

REFERENCES:
patent: 4003033 (1977-01-01), O'Keefe et al.
patent: 4059851 (1977-11-01), Nutter et al.
patent: 4179737 (1979-12-01), Kim
patent: 4298933 (1981-11-01), Shimokawa
patent: 4365294 (1982-12-01), Stokken
patent: 4453214 (1984-06-01), Adcock

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