Data processing system having multiple buses

Details Data processing system having multiple buses Data processing system having multiple buses

1980-10-14

1984-06-26

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1300, G06F 900

Patent

active

044569653

ABSTRACT:
A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.

REFERENCES:
patent: 3210733 (1965-10-01), Terzian et al.
patent: 3374466 (1968-03-01), Hanf et al.
patent: 3757306 (1973-09-01), Boone et al.
patent: 4152762 (1979-05-01), Bird et al.
patent: 4266270 (1981-05-01), Daniels et al.
patent: 4296469 (1981-10-01), Gunter et al.
patent: 4300194 (1981-11-01), Bradley et al.

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