Data processing system having load dependent bus timing

Details Data processing system having load dependent bus timing Data processing system having load dependent bus timing

1995-06-07

1997-02-18

Eng, David Y.

Boots, shoes, and leggings

3642384, 3649421, G06F 13372

Patent

active

056049153

ABSTRACT:
A data processing system in which timing of data transfer operations are adjusted in response to bus load variation is disclosed herein. The data processing system includes a microprocessor having a sensing circuit, and a driver circuit disposed to impress a signal upon a control line. The control line is also connected to the sensing circuit, as well as to one or more devices external to the microprocessor. The sensing circuit is configured to monitor a response time required for the signal impressed upon the control line to reach a predetermined electrical level, wherein the response time is a function of the number of devices coupled to the control line. The microprocessor is disposed to adjust the timing of data transfer between the microprocessor and the one or more devices external to the microprocessor based upon the monitored response time.

REFERENCES:
patent: 3849765 (1974-11-01), Hamano
patent: 4217637 (1980-08-01), Faulkner et al.
patent: 5339448 (1994-08-01), Tanaka et al.

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