Data processing system having four phase clocks generated separa

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307480, 307262, 307303, 328 63, H03K 513, H03K 1900

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active

051245710

ABSTRACT:
A digital system generates a single-phase master clock and distributes it to multiple cards and chips incorporating the functional logic of the system. A circuit in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.

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patent: 4239982 (1980-12-01), Smith et al.
patent: 4564953 (1986-01-01), Werkimg
patent: 4691124 (1987-09-01), Ledzius et al.
patent: 4866397 (1989-09-01), Kimyacioglu

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