Data processing system having error detection and correction cir

Details Data processing system having error detection and correction cir Data processing system having error detection and correction cir

1978-09-01

1980-05-06

Atkinson, Charles E.

Excavating

3401461AL, G06F 1112

Patent

active

042013372

ABSTRACT:
A data processing system implemented in LSI includes error detection and correction (EDC) circuits operating either in an error correction code (ECC) mode by generating ECC parity bits, or a byte parity mode by generating or checking byte parity bits. Each EDC circuit is identical and is capable of delivering identical control signals to byte sliced memory interface chips for purposes of error correction. The EDC circuits may be used individually with a 32 bit data bus or may be combined for use with a 64 bit data bus.

REFERENCES:
patent: 3568153 (1971-03-01), Kurtz et al.
patent: 3836957 (1974-09-01), Duke et al.
patent: 3893071 (1975-07-01), Bossen et al.
patent: 3949208 (1976-04-01), Carter
patent: 4077565 (1978-03-01), Nibby, Jr. et al.
patent: 4139148 (1979-02-01), Sheuneman et al.

Affiliated with

Also associated with

Rating

Data processing system having error detection and correction cir does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing system having error detection and correction cir, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system having error detection and correction cir will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1001441