Data processing system having dual arbiter for controlling acces

Details Data processing system having dual arbiter for controlling acces Data processing system having dual arbiter for controlling acces

1990-03-16

1991-08-06

Fleming, Michael R.

Boots, shoes, and leggings

36424292, 364270, 3642707, 3642703, G06F 946

Patent

active

050382764

ABSTRACT:
A data processing system having a dual arbiter for controlling access to a system bus where two processors, each clocked by one of two timing signals having equal periods but out of phase by half a period, operate synchronously each to the other, but outphased by the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.

REFERENCES:
patent: 4229791 (1980-10-01), Levy
patent: 4817066 (1989-03-01), Lewis

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