Data processing system having data multiplex control bus cycle

Details Data processing system having data multiplex control bus cycle Data processing system having data multiplex control bus cycle

1979-01-31

1981-09-29

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 300

Patent

active

042926688

ABSTRACT:
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

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Nissim, J., "DMA Controller Capitalizes on Clock Cycles to Bypass CPU," Computer Design, Jan. 1978, pp. 118-124.

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