Boots – shoes – and leggings
Patent
1979-02-09
1983-05-10
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 906
Patent
active
043832954
ABSTRACT:
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.
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Bradley John J.
Darden Boyd E.
Miller Robert C.
Miu Ming T.
Shen Jian-Kuo
Honeywell Information Systems Inc.
Linnell William A.
Prasinos Nicholas
Zache Raulfe B.
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