Boots – shoes – and leggings
Patent
1979-01-31
1982-03-23
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 300
Patent
active
043216650
ABSTRACT:
In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.
REFERENCES:
patent: 3490013 (1970-01-01), Lawrance et al.
patent: 3729713 (1973-04-01), Irwin
patent: 4103329 (1978-07-01), Davis et al.
patent: 4109310 (1978-08-01), England et al.
Bradley John J.
King Richard L.
Miller Robert C.
Miu Ming T.
Shen Jian-Kuo
Honeywell Information Systems Inc.
Linnell William A.
Prasinos Nicholas
Reiling Ronald T.
Zache Raulfe B.
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