Data processing system having an on-chip background debug...

Data processing: generic control systems or specific application – Generic control system – apparatus or process – Having preparation of program

Reexamination Certificate

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Details

C714S030000, C714S038110, C717S124000

Reexamination Certificate

active

06823224

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to data processing systems, and more particularly, to data processing systems having on-chip background debug systems.
RELATED ART
In order to reduce power consumption, modem data processing systems often allow the application program to adjust the system clock speed or even stop the oscillator. In some cases, these actions require a host development system to adjust its communication speed to adapt to these changes within the target data processing system. In the cases where the target system oscillator is stopped, background communications are also stopped, thus preventing normal debugging operations such as reading or writing target system memory locations. Therefore, a need exists to allow normal debugging operations while the application program stops or adjusts the system clock speed. A need also exists for a host development system to determine the correct clock speed for background communications with the target data processing system.


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Copy of related U.S. Patent Application SC11064THentitled, “Data Processing System With On-Chip Fifo For Storing Debug Information and Method Therefor”, (17 pgs.), filed on Feb. 16, 2001.

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