Data processing system having an intermediate buffer memory

Details Data processing system having an intermediate buffer memory Data processing system having an intermediate buffer memory

1977-10-28

1980-01-01

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

041819373

ABSTRACT:
In a data processing system having an intermediate buffer memory provided between a large space main memory and small space, high speed buffer memories of a plurality of processors, a data block of the intermediate buffer memory to be replaced with a data block of the main memory is determined by utilizing LRU (Least Recently Used) algorithm as well as copy flags employed in buffer invalidation processing. In the intermediate buffer memory, a data block that the number of its copy flags in the ON state is smaller than any other data blocks, is selected as the data block to be replaced. The fact that the number of copy flags in the ON state implies that the data block is not frequently used by the processors. Replacement of such a data block alleviates the burden of the buffer invalidation processing imposed on the intermediate buffer memory.

REFERENCES:
patent: 3848234 (1974-11-01), MacDonald
patent: 3886525 (1975-05-01), Brown et al.
patent: 3938097 (1976-02-01), Niguette
patent: 3984818 (1976-10-01), Gnadeberg et al.
patent: 4001786 (1977-01-01), Boehm
patent: 4050059 (1977-09-01), Williams et al.

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