Data processing system having an instruction pipeline for proces

Details Data processing system having an instruction pipeline for proces Data processing system having an instruction pipeline for proces

1980-07-25

1983-08-09

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 938

Patent

active

043982450

ABSTRACT:
A transfer instruction to be executed by a data processor includes a first operand representing a transfer-in address and a second operand representing a transfer-out address. Since the number of bytes transferred at a time is determined by a particular data processor used, a plurality of number of transfers are required to transfer the total data bytes, and first and second operand addresses must be calculated for each transfer. In a pipeline controlled data processor in the present invention, a circuit for calculating the first operand address is separately provided and this circuit is utilized in the first operand address calculation for second and subsequent data transfer operation so that the address calculation step is completed in one cycle of the pipeline control.

REFERENCES:
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 3988719 (1976-10-01), Whitby et al.
patent: 4149244 (1979-04-01), Anderson et al.

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