Data processing system having an apparatus for exception trackin

Details Data processing system having an apparatus for exception trackin Data processing system having an apparatus for exception trackin

1998-02-13

2000-10-03

Coleman, Eric

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712244, G06F 938

Patent

active

061287229

ABSTRACT:
An apparatus for integer exception register (XER) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, integer instructions that use or update the XER may be executed out-of-order using the XER renaming mechanism. Any instruction that updates the XER has an associated instruction identifier (IID) stored in a register. Subsequent instructions that use data in the XER use the stored IID to determine when the XER data has been updated by the execution of the instruction corresponding to the stored IID. As each instruction that updates XER data is executed, the data is stored in an XER rename buffer. Instructions using XER data then obtain the updated, valid, XER data from the rename buffer. In this way, these instructions can obtain valid XER data prior to completion of the preceding instructions. The XER data is retrieved from the XER rename buffer by indexing into the buffer by using an index derived from the stored IID. Because the updated XER data is available in the rename buffer before the updating instruction completes, out-of-order execution of instructions using or updating XER data is thereby realized.

REFERENCES:
patent: 5751985 (1998-05-01), Shen
patent: 5778219 (1998-07-01), Amerson

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