Boots – shoes – and leggings
Patent
1980-04-25
1983-08-09
Thomas, James D.
Boots, shoes, and leggings
G06F 930
Patent
active
043982433
ABSTRACT:
A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different level of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
REFERENCES:
patent: 3422401 (1969-01-01), Lucking
patent: 3710324 (1973-01-01), Cohen
patent: 3991404 (1976-11-01), Brioschi
patent: 4038533 (1977-07-01), Dummermuth
patent: 4099229 (1978-07-01), Kancler
patent: 4155119 (1979-05-01), DeWard et al.
A. Tanenbaum, Structured Computer Organization, textbook, 1976, Prentice-Hall, pp. 72-79.
Henry Carl
Holberger Kenneth D.
Veres James E.
Ziegler Michael L.
Data General Corporation
O'Connell Robert F.
Thomas James D.
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