Data processing system having a switching network connecting mul

Details Data processing system having a switching network connecting mul Data processing system having a switching network connecting mul

1992-09-14

1996-04-23

Lee, Thomas C.

Boots, shoes, and leggings

3642382, 3642393, 3642403, 364DIG1, G06F 1300

Patent

active

055112293

ABSTRACT:
A data processing apparatus includes a first (k.times.m)-bit data bus wherein k is a byte count and m is a bit length of one byte, a plurality of m-bit I/O peripheral devices at least one which is connected to two or more of m-bit data buses belonging to a first group consisting of first to k-th m-bit data buses obtained by dividing the first (k.times.m)-bit data bus into the first to k-th m-bit data buses; a second (k.times.m)-bit data bus, a (k.times.m)-bit I/O central processing unit connected to the second (k.times.m)-bit data bus which is divided into (k+1)-th m-bit data buses consisting of a second group of m-bit data buses; a data path switching circuit connected between the first and second (k.times.m)-bit data buses which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices and the CPU, and a transmission control circuit for generating control signals responsive to a demand of data transmission from said CPU. The m-bit I/O peripheral devices, first and second data buses, data path switching circuit and transmission control circuit can be integrated on an extended board.

REFERENCES:
patent: 3984819 (1976-10-01), Anderson
patent: 4447878 (1984-05-01), Kinnie et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4845611 (1989-07-01), Turlakov et al.
patent: 4965723 (1990-10-01), Kirk et al.
patent: 5220651 (1993-06-01), Larson

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