Data processing system having a memory with both a high speed op

Details Data processing system having a memory with both a high speed op Data processing system having a memory with both a high speed op

1993-12-20

1998-04-07

Swann, Tod R.

Boots, shoes, and leggings

364DIG1, 364707, 36518907, 365227, 395479, 395490, 395494, G06F 1200, G06F 1300

Patent

active

057375666

ABSTRACT:
A data processing system having a memory with a low power operating mode and a method of operation is described. An static random access memory (SRAM) (18) having a low power operating mode is provided for a data processing system (10). A programmable control bit is used for switching the SRAM (18) from a one clock cycle operating mode to a two clock cycle, or low power, operating mode. Initially, during the two cycle operating mode, only a bus interface unit (41) is active. During the first cycle, an address is compared to determine if the address is a valid address. If the address is valid, address decoders (42) are enabled, and a data transfer is completed on the second clock cycle. If the address is not valid, the address decoders (42) remain disabled and memory array (43) remains in a quiescent state consuming minimum power. During one cycle mode, the SRAM (18) decodes every address in order to respond in one clock cycle to a valid address.

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