Data processing system having a function of changing bus width

Details Data processing system having a function of changing bus width Data processing system having a function of changing bus width

1994-12-27

1998-06-09

Teska, Kevin J.

Boots, shoes, and leggings

3642403, 3642408, 3642604, 364DIG1, G06F 1342

Patent

active

057649502

ABSTRACT:
In a microcomputer, a high-order address bus of a control processing unit (CPU) is coupled to a first input of an address selector and an address latch having an output coupled to a second input of the address selector. An output of the address selector is connected to one input of a multiplexer having the other input connected to a high-order data bus of the CPU and an output connected to high-order address/data bus terminals. In the case that the microcomputer is coupled to only 8-bit external memories, the high-order address is outputted through the high-order address/data bus terminals during a period of accessing the external memory, and the address latch and the address selector are controlled to output the high-order address latched in the address latch through the high-order address/data bus terminals during a period of executing no access to the external memory.

REFERENCES:
patent: 4716527 (1987-12-01), Graciotti
patent: 4831514 (1989-05-01), Turlakov et al.
patent: 5307469 (1994-04-01), Mann
patent: 5335340 (1994-08-01), Strong
patent: 5341481 (1994-08-01), Tsukamoto

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