Data processing system having a data memory interlock coherency

Details Data processing system having a data memory interlock coherency Data processing system having a data memory interlock coherency

1988-04-01

1990-12-11

Fleming, Michael R.

Boots, shoes, and leggings

364900, 3642434, 36424341, 3642468, 3642384, 3649642, 3649692, 364968, G06F 1212, G06F 1214

Patent

active

049774980

ABSTRACT:
This invention is directed to a memory system that determines which blocks of a set of associative blocks in cache memory are unavailable for replacement. This is accomplished by operating the memory system to maintain a duplicate set of tags which track block ownership for this cache pursuant to a "snoopy" protocol. In addition, the cache system maintains a bit associated with each memory address to indicate whether any data blocks resident in it have been locked. The interlock status of the data blocks in the cache is not communicated to the memory system. Once a block is locked, it cannot be allocated for replacement until it is unlocked. When the cache system encounters a locked block, it skips over that block and allocates the next block of the associative blocks. From this, the memory system infers, by means of a replacement algorithm, that block is being locked and, therefore, cannot be replaced. This enables the memory system to implement an irregular replacement policy for this cache when the block to be replaced is owned and locked.

REFERENCES:
patent: 4513367 (1985-04-01), Chan et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4775955 (1988-10-01), Liu
patent: 4885680 (1989-12-01), Anthony et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.

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