Patent
1992-01-30
1994-03-29
MacDonald, Allen R.
395 24, G06F 1540
Patent
active
052992861
ABSTRACT:
Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n.times.n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses. A plurality of digital-analog converters, one for each column of the array of synapses, are connected to the random access memory for converting the digital voltage values for weighting the synapses into analog voltage values. The digital-analog converters provide respective outputs to the weighting terminals of the synapses of a column via respective electronic switches for each synapse. Each row of the array includes a bistable circuit for driving the respective electronic switches under the control of a control section which also provides function commands and data to the random access memory.
REFERENCES:
patent: 5039870 (1991-08-01), Engeler
patent: 5039871 (1991-08-01), Engeler
patent: 5047655 (1991-09-01), Charmbost et al.
patent: 5065132 (1991-11-01), Taddiken et al.
patent: 5072130 (1991-12-01), Dobson
patent: 5140531 (1992-08-01), Engeler
patent: 5146542 (1992-09-01), Engeler
patent: 5148514 (1992-09-01), Arima et al.
Eberhardt, "Design of Parallel Hardware Neural Network Systems From Custom Analog VLSI" Budding Block Chips IJCNN 1989, vol. 2, pp. II-183-190.
Murry et al., "Asynchronous VLSI Neural Networks Using Pulse-Stream Arithmetic," IEEE Journal of Solid State Circuits, vol. 23 #3, Jun. 1988, pp. 688-697.
Imondi Giuliano
Marotta Giulio
Porrovecchio Giulio
Savarese Giuseppe
Talamonti Luciano
Davis George
Donaldson Richard L.
Hiller William E.
MacDonald Allen R.
Texas Instruments Incorporated
LandOfFree
Data processing system for implementing architecture of neural n does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system for implementing architecture of neural n, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system for implementing architecture of neural n will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-799058