Data processing system controlling bus access to an arbitrary si

Details Data processing system controlling bus access to an arbitrary si Data processing system controlling bus access to an arbitrary si

1995-09-11

1998-01-06

Swann, Tod R.

395485, 395478, 395496, 39549701, 395490, 395411, 395420, 39542101, 395287, 395291, 395294, 395296, 395301, 395303, 395309, 395809, 395879, 395728, 395564, G06F 1300

Patent

active

057064695

ABSTRACT:
A novel data processing system is disclosed. Least significant bits of an address of a to-be-accessed memory of a number corresponding to a minimum specified range of a plurality of to-be-controlled memory areas each specified in an arbitrary size in advance are masked by mask bits. The access address with a predetermined number of least significant bits thereof masked is compared with each head address of a plurality of the memory areas to be controlled. It is decided in which of the memory areas to be controlled the access address is included. The memory access is controlled by access control data set for each memory area to be controlled. Further, the plurality of memory areas to be controlled are arranged in the order of priority. The to-be-controlled memory areas of higher priority are removed from the whole of the memory areas, whereby discontinuous memory areas are treated as a single memory area to be controlled.

REFERENCES:
patent: 4945472 (1990-07-01), Sakamura et al.
patent: 5300811 (1994-04-01), Suzuki et al.
80960CA User's Manual, 1989, pp.10-12 and 10-13, Intel Corporation.

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