Data processing system capable of performing vector/matrix proce

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364730, G06F 738

Patent

active

050383124

ABSTRACT:
An arithmetic processing unit which speeds up arithmetic operations performed up on vectors, matrices or a vector and a matrix, and is coupled to a central processing unit. The arithmetic unit includes a program memory for storing a microprogram corresponding to a macro-instruction code fed from the central processing unit, wherein each macro-instruction is representative of an arithmetic operation. Within the arithmetic unit, operand codes are transferred from an internal register array to operand registers assigned to an augend and an addend, or a multiplicand and a multiplier for calculations carried out by an arithmetic and logic unit. The operand codes for the arithmetic operation are successively transferred to the internal register array prior to the execution of the macro-instruction codes, so that the arithmetic processing unit completes each task without the need for interruptions to receive operands.

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