Boots – shoes – and leggings
Patent
1984-10-10
1987-05-12
Williams, Archie E.
Boots, shoes, and leggings
G06F 1314, G06F 1340
Patent
active
046654836
ABSTRACT:
Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time. If I/OP memory access requests are pending, the control unit grants access to the I/OP on a priority basis, activates a memory cycle and monitors in time relation with the memory cycle if other I/OP memory access requests are pending, further granting memory access without delay at the end of the memory cycle. Absent further I/O memory access requests, the control unit resynchronizes its memory access request monitoring with the CPU internal cycles.
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Ciacci Franco
Pizzoferrato Vincenzo
Tessera Giancarlo
Grayson George
Honeywell Information Systems Italia
Lee Thomas C.
Linnell William A.
Solakian John S.
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