Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-07-14
2004-08-17
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S394000, C370S421000, C370S509000, C370S519000
Reexamination Certificate
active
06778537
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-201969, filed Jul. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a data processing system for handling digital data, such as digital broadcast programs, and a time stamp creating method used in the system.
With the recent advancement in computer technology, various multimedia-compatible electronic apparatuses have been developed. They include digital videoplayers, set-top boxes, digital TVs, digital Video Cassette Recorders (VCRs), and personal computers. This type of electronic equipment can deal with various types of audio/video data supplied by satellite broadcasting or the like. The audio/video data are encoded by a moving-picture high-efficient coding scheme called Moving Picture Experts Group 2 (MPEG 2). Thereafter, the encoded data are transmitted to each home in the form of digital data streams known as transport streams.
To decode and reproduce the digital data streams transmitted in real time from a broadcasting station, it is necessary to synchronize the system clock of the decoder on the reception side with the system clock on the transmission side by using the Program Clock Reference (PCR) included as a synchronizing reference clock in the digital data streams. The reason for this is that all the presentation timing and decode timing of audio/video data are controlled on the basis of the system clock to prevent a time lag between the system clock on the transmission side and that on the reception side and such a time lag would cause the display to be distorted or the buffer on the decoder side to undergo overflow or underflow.
In the case of a receiving device where a tuner section for receiving the digital data streams from a broadcasting,station and a decoder section are placed in the same set, the clock system of the decoder can be corrected with relative ease. The reason for this is that the PCR included in the digital stream data is transmitted periodically such that the PCR can be transmitted from the tuner section to the decoder section without delay.
A problem arises when the received digital stream data is sent to the decoder by way of an IEEE 1394 serial bus. The IEEE 1394 serial bus has a transfer mode guaranteeing real-time features known as isochronous transfer and can transfer transport packets in real time. Even when the isochronous transfer is used, jitters cause a difference in transmission delay between the transport packets. If the difference in transmission delay causes variations in the arrival time of the PCRs, this leads to fluctuations in the system clock on the decoder side, which prevents the system clock on the decoder side from being synchronized with the system clock on the broadcasting station side.
The standard to solve the problem is IEC 61883. IEC 16883 specifies a time stamp called a source packet header (SPH) to be added to a transport packet and then transmitted. In the 1394 Link on the transmission side, the time a transport packet to be transmitted has arrived is inserted into the source packet header and then transmitted. In the 1394 Link on the reception side, the timing of the transport packet on the transmission side is restored using a timing adjusting circuit (pacer) specified by IEC 61883. That is, when the tuner is connected to the decoder via a 1394 serial bus at the 1394 Link provided in the tuner, a time stamp is added to a transport packet and then the resulting packet is sent to the decoder, which makes it possible to restore, on the decoder side, the timing of the packet transmitted from the broadcasting station and received by the tuner.
However, when a tuner for digital satellite broadcasting is implemented in a personal computer (PC), the following problem arises.
In the PC, the digital data streams received by the tuner are usually transferred to the 1394 Link via the CPU. In this case, the digital data streams received by the tuner have to be passed through the internal bus (Peripheral Component Interface (PCI) bus and others) once. The present PC architecture, however, has no mechanism for guaranteeing real-time transactions or the like on the internal bus. Therefore, it is impossible to transfer the received data to the 1394 Link, while keeping the timing of the digital data streams from the broadcasting station received by the tuner.
In this case, the time the transport packet arrives at the 1394 Link in the PC varies significantly from packet to packet. Thus, even if a source packet header is added to the transport packet at the 1394 Link and transmitted to the decoder on the 1394 serial bus, it is utterly impossible to restore, on the decoder side, the timing of the data transmitted from the broadcasting station.
Generally, an IEC 61883 timing adjusting circuit is not provided in the 1394 Link for the PC. For this reason, it is difficult for the PC to restore the timing of the digital data streams sent by way of the 1394 serial bus. This becomes a problem when the digital data streams recorded in a storage medium are transmitted again via the 1394 serial bus to the decoder, after the digital data streams sent via the 1394 serial bus have been recorded in the storage medium of the PC.
In other words, when the digital data streams are recorded in the storage medium, a process is needed in which the arrival time of the transport packets whose timing has been adjusted by the pacer are recorded together with the transport packets in the storage medium, and on reproduction, a source packet header is generated using the recorded arrival time.
Because the PC has no pacer as described above, it is impossible to restore the timing of the received transport packets exactly. Consequently, the exact arrival time of the transport packets cannot be recorded, therefore, even if the transport packets have been recorded., it is impossible to send them properly via the 1394 serial bus.
BRIEF SUMMARY OF THE INVENTION
It is, accordingly, an object of the present invention to provide a data processing system and a time stamp creating method which enable a correct time stamp to be always created even in a system without a mechanism for guaranteeing real-time features, such as a PC, and are suitable for the processing of audio/video data required to have real-time features.
The foregoing object is accomplished by providing a data processing system for adding a time stamp to compensate for the corresponding transmission delay difference to each of transmission packets constituting a digital data stream to be transmitted to an external node and for transmitting the resulting packets, the data processing system comprising: an internal bus; digital data receiving means connected to the internal bus and for adding time information indicating the corresponding reception time to each of the packets constituting a digital data stream externally received and for outputting the resulting packets onto the internal bus; and means connected to the internal bus for receiving packets to which the time information has been added and for creating a time stamp to be added to a transmission packet to be transmitted to the external node on the basis of the time information in each of the packets received.
In the data processing system, when digital stream data transmitted from a broadcasting station or the like is received, the receiving means adds time information indicating the corresponding reception time to each of the packets constituting the received digital data stream and then outputs the resulting packets onto the internal bus. Because the receiving means adds the reception time to each packet before outputting them onto the internal bus, the reception side that receives the digital data stream from the receiving means via the internal bus can know the timing of the digital stream data from the broadcasting station received by the receiving means. Thus, on the basis of the reception time difference b
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nguyen Van
Olms Douglas
LandOfFree
Data processing system and time stamp creating method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system and time stamp creating method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system and time stamp creating method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3314884