Data processing system and method using cache miss address predi

Details Data processing system and method using cache miss address predi Data processing system and method using cache miss address predi

1995-03-31

1997-12-23

Gossage, Glenn

395460, 395464, 395463, 395486, 39542103, G06F 1200, G06F 1300

Patent

active

057014264

ABSTRACT:
A data processing system which employs a cache memory feature and a method for lowering the cache miss ratio for called operands in the data processing system are disclosed. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The efficiency of the method and apparatus is improved by managing the priority of the block stored in cache memory such that a block received from main memory as a result of a prediction is forced to "least recently used" (LRU) status. In this manner, if the prediction has been incorrect, the incorrectly predicted block is replaced by the next block summoned from main memory rather than conventionally working its way down a priority stack before it is discarded.

REFERENCES:
patent: 4853840 (1989-08-01), Shibuya
patent: 5093777 (1992-03-01), Ryan
patent: 5367656 (1994-11-01), Ryan
patent: 5423048 (1995-06-01), Jager

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