Data processing system and method thereof

Details Data processing system and method thereof Data processing system and method thereof

1995-03-21

1998-04-07

Treat, William M.

395800, G06F 9302

Patent

active

057375860

ABSTRACT:
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

REFERENCES:
patent: 3287703 (1966-11-01), Slotnick
patent: 3796992 (1974-03-01), Nakamura et al.
patent: 4463445 (1984-07-01), Grimes
patent: 4470112 (1984-09-01), Dimmick
patent: 4488218 (1984-12-01), Grimes
patent: 4546428 (1985-10-01), Morton
patent: 4809169 (1989-02-01), Sfarti et al.
patent: 5067095 (1991-11-01), Peterson et al.
patent: 5073867 (1991-12-01), Murphy et al.
patent: 5083285 (1992-01-01), Shima et al.
patent: 5086405 (1992-02-01), Chung et al.
patent: 5140523 (1992-08-01), Frankel et al.
patent: 5140530 (1992-08-01), Guha et al.
patent: 5140670 (1992-08-01), Chua et al.
patent: 5146420 (1992-09-01), Vassiliadis et al.
patent: 5148515 (1992-09-01), Vassiliadis et al.
patent: 5150327 (1992-09-01), Matsushima et al.
patent: 5150328 (1992-09-01), Aichelmann, Jr.
patent: 5151874 (1992-09-01), Jeong et al.
patent: 5151971 (1992-09-01), Jousselin et al.
patent: 5152000 (1992-09-01), Hillis
patent: 5155389 (1992-10-01), Fartek
patent: 5155699 (1992-10-01), Chung et al.
patent: 5165009 (1992-11-01), Watanabe et al.
patent: 5165010 (1992-11-01), Masuda et al.
patent: 5167008 (1992-11-01), Engeler
patent: 5168573 (1992-12-01), Fossum et al.
patent: 5175858 (1992-12-01), Hammerstrom
patent: 5182794 (1993-01-01), Gasperi et al.
patent: 5197030 (1993-03-01), Akaogi et al.
patent: 5197130 (1993-03-01), Chen et al.
patent: 5226171 (1993-07-01), Hall et al.
patent: 5230057 (1993-07-01), Shido et al.
patent: 5440702 (1995-08-01), Brewer et al.
MC68000 8-/16-/32- Bit Microprocessor User's Manual, Eighth Edition, pp. 4-1 through 4-4; 4-8 through 4-12.
MC68020 32-BIT Microprocessor User's Manual, Fourth Edition, pp. 3-12 through 3-23.
Introduction to Computer Architecture written by Harold S. Stone et al. and published by Science Research Associates, Inc. in 1975, pp. 326 through 355.
"A VLSI Architecture for High-Performance, Low-Cost, On-chip Learning" by D. Hammerstrom for Adaptive Solutions, Inc., Feb. 28, 1990, pp. II-537 through II-544.
"CNAPS-1064 Preliminary Data CNAPS-1064 Digital Neural Processor" published by Adaptive Solutions, Inc. pp. 1-8.
DSP56000/DSP56001 Digital Signal Processor User's Manual, Rev. 1, published by Motorola, Inc. pp. 2-9 through 2-14, 5-1 through 5-21, 7-8 through 7-18.
"M-Structures: Ext. a Parallel, Non-strict, Functional Lang. with State" by Barth et al., Comp. Struct. Group Memo 327 (MIT), Mar. 18, 1991, pp. 1-21.
"A Pipelined, Shared Resource MIMD Computer" by B. Smith et al. and published in the Proceedings of the 1978 International Conference on Parallel Processing, pp. 6-8.
M68000 Family Programmer's Reference Manual published by Motorola, Inc. in 1989, pp. 2-71 through 2-78.
"The DSP is being reconfigured" by Chappell Brown and published in Electronic Engineering Times, Monday, Mar. 22, 1993, Issue 738, p. 29.
DSP56000/56001 Digital Signal Processor User's Manual published by Motorola, Inc. pp. 2-4 and 2-5, 4-6 and 4-7.
MC68340 Integrated Processor User's Manual published by Motorola, Inc. in 1990, pp. 6-1 through 6-22.
Transputer Architecture Technical Overview published by INMOS in Sep. 1985.
Product Description of the IMS T414 Transputer published by INMOS in Sep. 1985.
Product Description of the IMS T212 Transputer published by INMOS in Sep. 1985.
Proceedings from the INMOS Transputer Seminar tour conducted in 1986, published in Apr. 1986.
"Control Data STAR-100 Processor Design" written by R.G. Hintz et al. and published in the Innovative Architecture Digest of Papers for COMPCOM 72 in 1972, pp. 1 through 4.
"An Introduction to the ILLIAC IV Computer" written by D. McIntyre and published in Datamation, Apr. 1970, pp. 60-67.
"The ILLIAC IV Computer" written by G. Barnes et al. and published in IEEE Transactions on Computers, vol. C-17, No. 8, Aug. 1968, pp. 746-757.
The ILLIAC IV The First Supercomputer written by R. Michael Hord and published by Computer Science Press, pp. 1-69.
"The Torus Routing Chip" published in Journal of Distributed Computing, vol. 1, No. 3, 1986, and written by W. Dally et al. pp. 1-17.
"A Microprocessor-based Hypercube Supercomputer" written by J. Hayes et al. and published in IEEE MICRO in Oct. 1986, pp. 6-17.
"ILLIAC IV Software and Application Programming" written by David J. Kuck and published in IEEE Transactions on Computers, vol. C-17, No. 8, Aug. 1968, pp. 758-770.
"Building a 512X512 Pixel-Planes System" by J. Poulton et al. and published in Advanced Research in VLSI, Proceedings of the 1987 Stanford Conference, pp. 57-71.
"Coarse-grain & fine-grain parallelism in the next generation Pixel-planes graphic sys." by Fuchs et al. and published in Parallel Processing for Computer Vision and Display, pp. 241-253.
"Pixel Planes: A VLSI-Oriented Design for 3-D Raster Graphics" by H. Fuchs et al. and publ. in the proc. of the 7th Canadian Man-Computer Comm. Conference, pp. 343-347.
"Pixel-Planes: Building a VLSI-Based Graphic System" by J. Poulton et al. and published in the proceedings of the 1985 Chapel Hill Conference on VLSI, pp. 35-60.
"Pixel-Planes 5: A Heterogenous Multiprocessor Graphics System Using Processor-Enhanced Memories" Fuchs et al. and published in Computer Graphics, vol. 23,No. 3,Jul. 1989,pp. 79-88.
"Parallel Processing In Pixel-Planes, a VLSI logic-enhanced memory for raster graphics" by Fuchs et al. published in the proceedings of ICCD' 85 held in Oct., 1985, pp. 193-197.
"Neural Networks Primer Part VII" published in Al Expert in May 1989 and written by Maureen Caudill, pp. 51 through 58.
"Neural Networks Primer Part VIII" published in Al Expert in Aug. 1989 and written by Maureen Caudill, pp. 61 through 67.
"Fast Spheres,Shadows,Textures,Transparencies, and Image Enhancements in Pixel Planes" by H. Fuchs et al. and published in Computer Graphics, vol. 19, No. 3, Jul. 1985, pp. 111-120.
"The Design of a Neuro-Microprocessor", published in IEEE Transactions on Neural Networks, on May 1993, vol. 4, No. 3, ISSN 1045-9227, pp. 394 through 399.
"ILLIAC IV Systems Characteristics and Programming Manual" published by Burroughs Corp. on Jun. 30, 1970, IL4-PM1, Change No. 1.
"Neural Networks Primer Part IV" published in Al Expert in Aug. 1988 and written by Maureen Caudill, pp. 61 through 67.
"Neural Networks Primer Part V" published in Al Expert in Nov. 1988 and written by Maureen Caudill, pp. 57 through 65.
"Neural Networks Primer Part VI" published in Al Expert in Feb. 1989 and written by Maureen Caudill, pp. 61 through 67.
"Neural Networks Primer Part I" published in Al Expert in Dec. 1987 and written by Maureen Caudill, pp. 46 through 52.
"Neural Networks Primer Part II" published in Al Expert in Feb. 1988 and written by Maureen Caudill, pp. 55 through 61.
"Neural Networks Primer Part III" published in Al Expert in Jun. 1988 and written by Maureen Caudill, pp. 53 through 59.
K.Asanovic,et al.,"SPERT:a VLIW/SIMD microprocessor for artificial neural network computations", published in 1992 by IEEE Computer Society Press, Conference Paper, pp. 178-190.
K.Asanovic, "SPERT:a VLIW/SIMD neuro-microprocessor", published in 1992 by IEEE, vol.4, pp. 577-582.
Daniel P. Siewiorek et al., "Computer Structures: Principles and Examples", Chapter 20, The Illiac IV System, Subsetted from Proc. IEEE, Apr. 1972, pp. 369-388, pub. by McGraw-Hill Book Co.
C. Gordon Bell et al., "Computer Structures: Readings and Examples", Chapter 27, The Illiac IV computer, IEEE Trans., C-17, Vol. 8, pp. 746-757, Aug.,1968, pub. by McGraw-Hill Book Co.

Affiliated with

Also associated with

Rating

Data processing system and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing system and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system and method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-25630